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AD9480 Datasheet(PDF) 7 Page - Analog Devices |
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AD9480 Datasheet(HTML) 7 Page - Analog Devices |
7 / 29 page AD9480 Rev. A | Page 6 of 28 SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted. Table 4. AD9480-250 Parameter Temp Test Level Min Typ Max Unit CLOCK Maximum Conversion Rate Full VI 250 MSPS Minimum Conversion Rate Full VI 20 MSPS Clock Pulse Width High (tEH) Full IV 1.2 2 ns Clock Pulse Width Low (tEL) Full IV 1.2 2 ns OUTPUT PARAMETERS Valid Time (tV)1 Full VI 1.9 ns Propagation Delay (tPD) Full VI 2.8 3.8 ns Rise Time (tR) 20% to 80% Full V 0.5 ns Fall Time (tF) 20% to 80% Full V 0.5 ns DCO Propagation Delay (tCPD) Full VI 1.9 2.7 3.7 ns Data-to-DCO Skew (tPD − tCPD) Full IV 0 0.1 0.6 ns Pipeline Latency 25°C VI 8 Cycles APERTURE Aperture Delay (tA) 25°C V 1.5 ns Aperture Uncertainty (Jitter) 25°C V 0.25 ps rms 1 Valid time is approximately equal to minimum tPD. CLOAD equals 5 pF maximum. TIMING DIAGRAM N–1 N N+1 N+8 N+9 N+10 N+11 tEH tEL 1/fS tA N–8 tPD 8 CYCLES tV N–7 N N+1 N+2 tCPD CLK+ CLK– DATA OUT DCO– DCO+ AIN Figure 2. Timing Diagram |
Similar Part No. - AD9480_17 |
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Similar Description - AD9480_17 |
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