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ADS8598HIPM Datasheet(PDF) 5 Page - Texas Instruments |
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ADS8598HIPM Datasheet(HTML) 5 Page - Texas Instruments |
5 / 64 page 5 ADS8598H www.ti.com SBAS829 – SEPTEMBER 2017 Product Folder Links: ADS8598H Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE DESCRIPTION NAME NO. RD/SCLK 12 DI Multi-function logic input pin (see the RD/SCLK (Input) section): this pin is an active-low ready input pin in parallel and parallel byte interface; this pin is a clock input pin in serial interface mode. REFCAPA 44 AO Reference amplifier output pin. This pin must be shorted to REFCAPB and decoupled to AGND using a low ESR, 10-µF ceramic capacitor. REFCAPB 45 AO Reference amplifier output pin. This pin must be shorted to REFCAPA and decoupled to AGND using a low ESR, 10-µF ceramic capacitor. REFGND 43, 46 P Reference GND pin. This pin must be shorted to the analog GND plane and decoupled with REFIN/REFOUT on pin 42 using a 10-µF capacitor. REFIN/REFOUT 42 AIO This pin acts as an internal reference output when REFSEL is high; this pin functions as input pin for the external reference when REFSEL is low; decouple with REFGND on pin 43 using a 10-µF capacitor. REFSEL 34 DI Active high logic input to enable the internal reference (see the REFSEL (Input) section). REGCAP1 36 AO Output pin 1 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor. REGCAP2 39 AO Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor. RESET 11 DI Active high logic input to reset the device digital logic (see the RESET (Input) section). STBY 7 DI Active low logic input to enter the device into one of the two power-down modes: standby or shutdown (see the Power-Down Modes section). (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Transient currents of up to 100 mA do not cause SCR latch-up. 6 Specifications 6.1 Absolute Maximum Ratings at TA = 25°C (unless otherwise noted) (1) MIN MAX UNIT AVDD to AGND –0.3 7.0 V DVDD to AGND –0.3 7.0 V Analog input voltage to AGND(2) –15 15 V Digital input to AGND –0.3 DVDD + 0.3 V REFIN to AGND –0.3 AVDD + 0.3 V Input current to any pin except supplies(2) –10 10 mA Temperature Operating –40 125 °C Junction, TJ 150 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except analog inputs ±2000 V Analog input pins only ±9000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 |
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