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P87C591VFA Datasheet(PDF) 3 Page - NXP Semiconductors |
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P87C591VFA Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 160 page  2000 Jul 26 3 Philips Semiconductors Preliminary Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 1 FEATURES 1.1 80C51 Related Features of the 8xC591 • Full static 80C51 Central Processing Unit available as OTP, ROM and ROMless • 16 Kbytes internal Program Memory expandable externally to 64 Kbytes • 512 bytes on-chip Data RAM expandable externally to 64 Kbytes • Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture & compare) • 10-bit ADC with 6 multiplexed analog inputs with fast 8-bit ADC option • Two 8-bit resolution, Pulse Width Modulated outputs • 32 I/O port pins in the standard 80C51 pinout • I2C-bus serial I/O port with byte oriented master and slave functions • On-chip Watchdog Timer T3 • Extended temperature range: −40 to +85°C • Accelerated (prescaler 1:1) instruction cycle time 500 ns @ 12 MHz • Operation voltage range: 5 V ± 5% • Security bits: – ROM version has 2 bits – OTP/EPROM version has 3 bits • 32 bytes Encryption array • 4 level priority interrupt, 15 interrupt sources • Full-duplex enhanced UART with programmable Baudrate Generator • Power Control Modes: – Clock can be stopped and resumed – Idle Mode – Power-down Mode • ADC active in Idle Mode • Second DPTR register • ALE inhibit for EMI reduction • Programmable I/O port pins (pseudo bi-directional, push-pull, high impedance, open drain) • Wake-up from Power-down by external interrupts • Software reset bit (AUXR1.5) • Low active reset pin • Power-on detect reset • Once mode 1.2 CAN Related Features of the 8xC591 • CAN 2.0B active controller, supporting 11-bit Standard and 29-bit Extended indentifiers • 1 Mbit/s CAN bus speed with 8 MHz clock achievable • 64 byte receive FIFO (can capture sequential Data Frames from the same source as required by the Transport Layer of higher protocols such as DeviceNet, CANopen and OSEK) • 13 byte transmit buffer • Enhanced PeliCAN core (from the SJA1000 stand-alone CAN2.0B controller) 1.2.1 PELICAN FEATURES • Four independently configurable Screeners (Acceptance Filters) • Each Screener has two 32-bit specifies: – 32-bit Match and – 32-bit Mask • 32-bits of Mask per Screener allows unique Group addressing per Screener • Higher layer protocols especially supported in Standard CAN format with: – Up to four, 11-bit ID Screeners that also Screen the two (2) Data Bytes – i.e., Data Frames are Screened by the CAN ID and by Data Byte content • Up to eight, 11-bit ID Screeners half of which also Screen the first Data Byte • All Screeners are changeable “on the fly” • Listen Only Mode, Self Test Mode • Error Code Capture, Arbitration Lost Capture, readable Error Counters |
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