ICS8735AM-21 datasheet(7/15 Pages) ETC

Part #	ICS8735AM-21

Description	700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

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8735AM-21

www.icst.com/products/hiperclocks.html

REV. D OCTOBER 27, 2003

7

Integrated

Circuit

Systems, Inc.

ICS8735-21

700MHZ, DIFFERENTIAL-TO-3.3V LVPECL

ZERO DELAY CLOCK GENERATOR

APPLICATION INFORMATION

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ V

CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8735-21 provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

CC, VCCA, and VCCO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 1 illustrates how

a 10

Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V

CCA pin.

POWER SUPPLY FILTERING TECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

10

Ω

V

CCA

10

µF

.01

µF

3.3V

.01

µF

V

CC

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

CC = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

R1

1K

C1

0.1u

R2

1K

Single Ended Clock Input

CLK

nCLK

VDD

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