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TCAN1043HGDMTRQ1 Datasheet(PDF) 9 Page - Texas Instruments |
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TCAN1043HGDMTRQ1 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 43 page 9 TCAN1043-Q1, TCAN1043H-Q1, TCAN1043HG-Q1, TCAN1043G-Q1 www.ti.com SLLSEV0 – OCTOBER 2017 Product Folder Links: TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) All typical values are at 25°C and supply voltages of VCC = 5 V. For dual supply devices VIO = 3.3 V. RL = 60 Ω. (2) The TXD dominant timeout (t(TXD_DTO)) disables the driver of the transceiver once the TXD has been dominant longer than t(TXD_DTO), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(TXD_DTO) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / t(TXD_DTO) 7.8 Switching Characteristics Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT DRIVER SWITCHING CHARACTERISTICS tpHR Propagation delay time, High TXD to Driver Recessive See Figure 15, Normal mode. RL = 60 Ω, CL = 100 pF, RCM = open 50 TBD ns tpLD Propagation delay time, Low TXD to Driver Dominant 40 TBD ns tsk(p) Pulse skew (|tpHR - tpLD|) 10 TBD ns tR Differential output signal rise time 45 TBD µs tF Differential output signal fall time 45 TBD µs tTXD_DTO Dominant Time Out(2) See Figure 14, RL = 60 Ω, CL = open 1.2 3.8 ms RECEIVER SWITCHING CHARACTERISTICS tpRH Propagation delay time, bus recessive input to high RXD See Figure 14, CL(RXD) = 15 pF Char Range: TBD if wider range needed to look at. Typical Conditions for DS: CANL = 1.5 V, CANH = 4 V. 50 TBD ns tpDL Propagation delay time, bus dominant input to RXD low output 50 TBD ns tR Output signal rise time (RXD) 8 TBD ns tF Output signal fall time (RXD) 8 TBD ns tBUS_DOM Dominant time out See Figure 17, RL = 60 Ω, CL = open 1.4 3.8 ms tCBF Bus fault detection time 45 Ω ≤ RCM ≤ 70 Ω, CL = open 1.9 µs Wake Terminal (Wake input) tWAKE_HT WAKE hold time Time required for LWU from a H to L or L to H on WAKE 5 50 µS Device Switching Characteristics tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant Normal Mode, See Figure 17, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 100 160 ns tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive 110 175 ns tMODE1 Mode change time See Figure 15 and Figure 16. Mode change time for leaving Sleep Mode to entering normal and silent mode after VCC and VIO have crossed UV thresholds 20 µs tMODE2 Mode change time Mode changes between Normal, Silent and Standby Modes, and Sleep to Standby Mode transition 10 µs tUV_RE-ENABLE Re-enable time after UV event Time for device to return to normal operation from UVVCC or UVVIO under voltage event 200 µs tPower_Up Power up time on VSUP See Figure 16 250 µs tWK_FILTER Bus time to meet Filtered Bus Requirements for Wake Up Request See Figure 17, sleep mode. 0.5 1.85 µs tWK_TIMEOUT Bus Wake-up timeout value 0.5 2 ms tUV Undervoltage filter time for VIO and VCC VIO ≤ UVVIO or VCC < UVVCC 159 340 ms tGo_To_Sleep Minimum hold time for transition to sleep mode EN = H and nSTB = L 5 50 µs FD Timing Parameters |
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