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SM561
Document #: 38-07021 Rev. *C
Page 3 of 8
Table 1. Frequency and Spread% Selection (Center Spread)
Tri-level Logic
With binary logic, four states can be programmed with two
control lines where as Tri-level Logic can program nine logic
states using two control lines. Tri-level Logic in the SM561 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0”. Pins 6 and 7 of the SM561
recognize a logic state by the voltage applied to the respective
pin. These states are defined as “0” (Low), “M” (Middle), and
“1” (One). Each of these states have a defined voltage range
that is interpreted by the SM561 as a “0”, “M,” or “1” logic state.
Refer to Table 1 for voltage ranges for each logic state. By
using two equal value resistors (typically 20K) the “M” state
can be easily programmed. Pins 6 or 7 can be tied directly to
ground or VDD for Logic “0” or “1,” respectively.
54 -108 M H z (L o w R a n g e )
In p u t
F re q ue nc y
(M H z )
S1 = M
S0 = M
(% )
S1 = M
S0 = 0
(% )
S1 = 1
S0 = 0
(% )
S1 = 0
S0 = 0
(% )
S1 = 0
S0 = M
(% )
54 - 60
3 .6
3.1
2.6
2.1
1.8
60 - 70
3 .5
3.0
2.5
2.0
1.7
70 - 80
3 .3
2.8
2.4
1.9
1.6
80 - 100
3 .0
2.5
2.1
1.7
1.4
10 0 - 1 0 8
2 .6
2.3
1.9
1.5
1.3
10 8 - 1 6 6 M H z (H ig h R a n g e)
In p u t
F re q ue nc y
(M H z )
S1 = 1
S0 = M
(% )
S1 = 0
S0 = 1
(% )
S1 = 1
S0 = 1
(% )
S1 = M
S0 = 1
(% )
18 0 - 1 2 0
2 .3
1.7
1.1
0.9
12 0 -130
2 .3
1.7
1.1
0.9
13 0 - 1 4 0
2 .3
1.7
1.1
0.9
14 0 - 1 5 0
2 .2
1.6
1.1
0.9
15 0 - 1 6 6
2 .1
1.5
1.0
0.8
S e lect th e
Fre que n c y a n d
C e n ter S p read %
de s ir e d a n d th en
set S 1 , S 0 as
in d icated .
S e lect th e
Fre que n c y a n d
C e n ter S p read %
de s ir e d a n d th en
set S 1 , S 0 as
in d icated .
VDD = 3.3 VDC
VDD = 3.3 VDC
VDD = 3.3 VDC
SM561
5
6
7
SM561
5
6
7
1.65 VDC
0 VDC
7
6
5
SM561
EX. 1
EX. 2
EX. 3
20K
20K
Figure 1.
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