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SN75LVDS387DGG Datasheet(PDF) 4 Page - Texas Instruments |
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SN75LVDS387DGG Datasheet(HTML) 4 Page - Texas Instruments |
4 / 18 page SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT |VOD| Differential output voltage magnitude RL = 100 Ω 247 340 454 ∆|VOD| Change in differential output voltage magnitude between logic states RL = 100 Ω,, See Figure 1 and Figure 2 – 50 50 mV VOC(SS) Steady-state common-mode output voltage 1.125 1.375 V ∆VOC(SS) Change in steady-state common-mode output voltage between logic states See Figure 3 – 50 50 mV VOC(PP) Peak-to-peak common-mode output voltage 50 150 mV ’LVDS387 Enabled, 85 95 ’LVDS389 Enabled, RL = 100 Ω , 50 70 ICC Supply current ’LVDS391 VIN = 0.8 V or 2 V 20 26 mA ICC Supply current ’LVDS387 Di bl d 0.5 1.5 mA ’LVDS389 Disabled, VIN =0VorVCC 0.5 1.5 ’LVDS391 VIN = 0 V or VCC 0.5 1.3 IIH High-level input current VIH = 2 V 3 20 µA IIL Low-level input current VIL = 0.8 V 2 10 µA IOS Short circuit output current VOY or VOZ = 0 V ±24 mA IOS Short-circuit output current VOD = 0 V ±12 mA IOZ High-impedance output current VO = 0 V or VCC ±1 µA IO(OFF) Power-off output current VCC = 1.5 V, VO = 2.4 V ±1 µA CIN Input capacitance VI = 0.4 sin (4E6πt) + 0.5 V 5 pF CO Output capacitance VI = 0.4 sin (4E6πt) + 0.5 V, Disabled 9.4 pF † All typical values are at 25 °C and with a 3.3-V supply. switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH Propagation delay time, low-to-high-level output 0.9 1.7 2.9 ns tPHL Propagation delay time, high-to-low-level output 0.9 1.6 2.9 ns tr Differential output signal rise time RL = 100 Ω 0.4 0.8 1 ns tf Differential output signal fall time RL = 100 Ω , CL = 10 pF, 0.4 0.8 1 ns tsk(p) Pulse skew (|tPHL – tPLH|) L See Figure 4 150 500 ps tsk(o) Output skew‡ 80 150 ps tsk(pp) Part-to-part skew§ 1.5 ns tPZH Propagation delay time, high-impedance-to-high-level output 6.4 15 ns tPZL Propagation delay time, high-impedance-to-low-level output See Figure 5 5.9 15 ns tPHZ Propagation delay time, high-level-to-high-impedance output See Figure 5 3.5 15 ns tPLZ Propagation delay time, low-level-to-high-impedance output 4.5 15 ns † All typical values are at 25 °C and with a 3.3-V supply. ‡ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together. § tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits. |
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