Data Sheet

AD7152/AD7153

Rev. A | Page 5 of 24

TIMING SPECIFICATIONS

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

See Figure 3.

SCL Frequency

0

400

kHz

0.6

µs

1.3

µs

0.3

µs

0.3

µs

0.6

µs

After this period, the first clock is generated.

0.6

µs

Relevant for repeated start condition.

0.1

µs

0.6

µs

0.01

µs

1.3

µs

1

Sample tested during initial release to ensure compliance.

2

All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs;

output load = 10 pF.

P

S

SCL

P

S

SDA

Figure 3. Serial Interface Timing Diagram