6

VFC101

®

FIGURE 2. Offset for Bipolar Input Voltages.

Mylar™, Teflon™ E. I. du Pont de Nemours & Co.

Integrator

Comparator

Clocked

Logic

Output

One-Shot

54

17

13

18

2

+V

CC

14

15

f

OUT

0 to f

Digital

Ground

12

11

–V

CC

16

Analog

Ground

5V

Reference

20

C

INT

0.1µF

+V

L

0.1µF

+V

CC

f

CLOCK

TTL/CMOS

I

1

+V

CC

0.1µF

–V

CC

–V

CC

1mA

7

9

10k

Ω

8

10k

Ω

16k

Ω

10

4k

Ω

6

V

IN

–5V

to

+5V

INSTALLATION AND

OPERATING INSTRUCTIONS

The integrator capacitor C

INT

(see Figure 1) affects the

magnitude of the integrator voltage waveform. Its absolute

accuracy is not critical since it does not affect the transfer

function. Figure 3 facilitates choosing an appropriate stan-

dard value to assure that the integrator waveform voltage is

within acceptable limits. Good dielectric absorption proper-

ties are required to achieve best linearity. Mylar™, polycar-

bonate, mica, polystyrene, Teflon™ and glass types are

appropriate choices. Choice will depend on the particular

value and size. Ceramic capacitors vary considerably from

type to type and some produce significant nonlinearities.

Polarized capacitors should not be used.

Deviation from the nominal recommended +1V to –0.75V

integrator voltage (as controlled by the integrator capacitor

value) is permissible and will have a negligible effect on

FIGURE 3. Integrator Capacitor Selection Graph.

+1V

–0.75V

10µ

1µ

0.1µ

0.01µ

1000p

100p

100

1k

10k

100k

1M

Full-Scale Frequency (Hz)

+2.5V

–1.9V

NOTE: (1)This is the maximum swing of the integrator output

voltage referred to the comparator noninverting input voltage.

+100mV

–75mV

10M

VFC operation. It may be desirable to deviate from the

suggested value. Smaller integrator voltages, for instance,

allow more “headroom” for averaging noisy input signals.

The VFC is a fully integrating input converter, able to reject

large levels of interfering noise. This ability is limited only

by the output voltage swing range of the integrator amplifier.

By setting a small integrator voltage swing using a large

integrator output saturation and loss of accuracy.

The maximum integrator voltage swing requirement is nearly

symmetrical about the comparator threshold voltage (see

Figure 5.) One-third greater swing is required above the

threshold than below it. Maximum demand on positive

integrator swing occurs at low scale, while the negative

swing is greatest just below full scale.

CLOCK INPUT

The clock input is TTL- and CMOS-compatible. Its input

threshold is approximately 1.4V (two diode voltage drops)

referenced to digital ground (pin 15). The clock “high” input

may be standard TLL or may be as high as +V

input has a high input impedance, so no special drivers are

required. Rise time in the transition region from 0.5V to 2V

must be less than 2

µs for proper operation.

OUTPUT

The frequency output is an open collector current-sink

transistor. Output pulses are active-low during the reset

integration period (see “Shortened Output Pulses”.)

Interface to a logic circuit normally uses a pull-up resistor to

the logic power supply. Selection of the pull-up resistor

should be made such that no more than 15mA flows in the

output transistor. The actual choice of the pull-up resistor

may depend on the full-scale frequency and the stray capaci-