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AD73322LYST-REEL Datasheet(PDF) 3 Page - Analog Devices |
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AD73322LYST-REEL Datasheet(HTML) 3 Page - Analog Devices |
3 / 49 page AD73322L Rev. A | Page 2 of 48 TABLE OF CONTENTS Specifications..................................................................................... 4 Current Summary......................................................................... 6 Signal Ranges ................................................................................ 7 Timing Characteristics ................................................................ 7 Timing Diagrams.......................................................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Terminology .................................................................................... 12 Abbreviations .............................................................................. 12 Typical Performance Characteristics and Functional Block Diagram ........................................................................................... 13 Functional Descriptions ................................................................ 14 Encoder Channels ...................................................................... 14 Programmable Gain Amplifier................................................. 14 ADC ............................................................................................. 14 Analog Sigma-Delta Modulator ............................................... 14 Decimation Filter........................................................................ 15 ADC Coding ............................................................................... 15 Decoder Channel........................................................................ 16 DAC Coding................................................................................ 16 Interpolation Filter ..................................................................... 16 Analog Smoothing Filter and PGA.......................................... 16 Differential Output Amplifiers ................................................. 16 Voltage Reference ....................................................................... 16 Analog and Digital Gain Taps................................................... 17 Digital Gain Tap.......................................................................... 18 Serial Port (SPORT) ................................................................... 18 SPORT Overview........................................................................ 18 SPORT Register Maps................................................................ 19 Master Clock Divider................................................................. 19 Serial Clock Rate Divider .......................................................... 19 Sample Rate Divider................................................................... 19 DAC Advance Register .............................................................. 20 Control Register A ..................................................................... 21 Control Register B...................................................................... 21 Control Register C...................................................................... 21 Control Register D ..................................................................... 22 Control Register E ...................................................................... 22 Control Register F ...................................................................... 22 Control Register G ..................................................................... 23 Control Register H ..................................................................... 23 Operation......................................................................................... 24 Resetting the AD73322L ........................................................... 24 Power Management ................................................................... 24 Operating Modes........................................................................ 24 Program (Control) Mode .......................................................... 24 Data Mode................................................................................... 25 Mixed Program/Data Mode...................................................... 25 Digital Loop-Back Mode........................................................... 25 SPORT Loop-Back Mode.......................................................... 25 Analog Loop-Back Mode .......................................................... 26 Interfacing ....................................................................................... 27 Cascade Operation..................................................................... 27 Performance .................................................................................... 29 Encoder Section.......................................................................... 29 Encoder Group Delay ................................................................ 30 Decoder Section ......................................................................... 30 On-Chip Filtering....................................................................... 31 Decoder Group Delay................................................................ 31 Design Considerations................................................................... 32 Analog Inputs ............................................................................. 32 Interfacing to an Electret Microphone .................................... 34 |
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