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74AHC1G00 Datasheet(PDF) 9 Page - NXP Semiconductors |
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74AHC1G00 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 2002 May 27 9 Philips Semiconductors Product specification 2-input NAND gate 74AHC1G00; 74AHCT1G00 AC WAVEFORMS handbook, halfpage MNA106 A, B input Y output tPHL tPLH VM VM Fig.5 The inputs (A and B) to output (Y) propagation delays. FAMILY VI INPUT REQUIREMENTS VM INPUT VM OUTPUT AHC1G GND to VCC 50% VCC 50% VCC AHCT1G GND to 3.0 V 1.5 V 50% VCC Fig.6 Load circuitry for switching times. handbook, halfpage VCC VI VO MNA101 D.U.T. CL RT PULSE GENERATOR Definitions for test circuit: CL = Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”). RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator. |
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