ADT75

Data Sheet

Rev. B | Page 6 of 24

TIMING SPECIFICATIONS AND DIAGRAM

improves the transfer rate but has a negative effect on the EMC behavior of the part.

Table 3.

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

Serial Clock Period, t

1

2.5

µs

Data In Setup Time to SCL High, t

2

50

ns

See Figure 2

Data Out Stable After SCL Low, t

3

0

0.92

ns

Data Out Stable After SCL Low, t

3

0

3.452

µs

SDA Low Setup Time to SCL Low (Start Condition), t

4

50

ns

See Figure 2

SDA High Hold Time After SCL High (Stop Condition), t

5

50

ns

See Figure 2

SDA and SCL Rise Time, t

6

300

ns

SDA and SCL Rise Time, t

6

1000

ns

SDA and SCL Fall Time, t

7

300

ns

See Figure 2

Capacitive Load for each Bus Line, C

B

400

pF

SCL

SDA

DATA IN

SDA

DATA OUT