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CS62180 Datasheet(PDF) 24 Page - Cirrus Logic |
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CS62180 Datasheet(HTML) 24 Page - Cirrus Logic |
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24 / 50 page  193E Timing Link data can be identified by RLCLK, which goes high for all odd numbered frames. RSIGFR is high for signaling frames, and low at all other times. RSIGSEL runs at twice the frequency of RMSYNC. Logical combination of RMSYNC and RSIGSEL provides a way to distinguish the 6 th, 12th, 18th, and 24th frames for external mul- tiplexing of signaling channels. RMSYNC is high for frames containing A and B signaling bits, and RSIGSEL is high for frames with A and C bits. Refer to Figure 16 for a timing dia- gram. SLC-96 ® Timing The CS62180B will output 36 bits of the DL on RLINK using RLCLK. RSIGSEL can be used to locate the DL bits. RSIGSEL will be held high in those frames where Fs bits and the last spoiler bit are present (frames 58 to 11). RSIGSEL is held low in all other frames (frames 12 to 57). RSIGFR is high for signaling frames, and low at all other times. RMSYNC is high for frames containing A signaling bits, and low for frames containg B bits. Refer to Figure 17 for a timing diagram. In SLC-96 ® mode, the start of a new multiframe occurs on the second rising edge of RMSYNC which occurs while RSIGSEL is high. A multiframe synchronization signal can be gen- erated from RMSYNC and RSIGSEL using the Frame RFSYNC 12 23 45 67 1 8 9 101112 2 3 45 67 18 9 10 11 12 2 3 4 5 6 7 1 8 9 RLINK RLCLK RSIGFR RSIGSEL RMSYNC Figure 18. T1DM Multiframe Receive Timing RMSYNC RFSYNC Data Link C1 C2 C3 C4 C5 C6 S4 M3 A1 S1 S2 S3 A2 Frame X 12 13 14 15 16 17 11 18 19 20 21 22 56 57 58 72 1 55 2 3 44 45 46 47 49 50 51 52 53 54 48 RLINK RSIGSEL RSIGFR AB A B B RLCLK C1 C2 C3 C4 C5 C6 M3 A1 A2 S1 S2 S3 S4 FS FS FS Figure 17. SLC-96 ® Multiframe Receive Timing CS62180B 24 DS225PP2 |
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Similar Description - CS62180 |
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