IS61LV12816

Integrated Silicon Solution, Inc. — 1-800-379-4774

7

Rev. A

11/30/00

-8 ns

-10 ns

-12 ns

-15 ns

Symbol

Parameter

Min.

Max

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

8

—

10

—

12

—

15

—

ns

CE to Write End

6.5

—

8

—

8

—

10

—

ns

Address Setup Time

6.5

—

8

—

8

—

10

—

ns

to Write End

Address Hold from Write End

0

—

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

0

—

ns

LB, UB Valid to End of Write

6.5

—

8

—

9

—

10

—

ns

WE Pulse Width (OE = HIGH)

5

—

7

—

8

—

10

—

ns

WE Pulse Width (OE = LOW)

6.5

—

8

—

10

—

11

—

ns

Data Setup to Write End

4

—

5

—

6

—

7

—

ns

Data Hold from Write End

0

—

0

—

0

—

0

—

ns

—

3

—

4

—

5

—

6ns

0

—

0

—

0

—

0

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V

to 3.0V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of

CE LOW and UB or LB, and WE LOW. All signals must be in valid

states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing

are referenced to the rising or falling edge of the signal that terminates the write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.