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AD6679BBPZRL7-500 Datasheet(PDF) 8 Page - Analog Devices |
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AD6679BBPZRL7-500 Datasheet(HTML) 8 Page - Analog Devices |
8 / 82 page Data Sheet AD6679 Rev. B | Page 7 of 81 Parameter1 Temperature Min Typ Max Unit SPURIOUS FREE DYNAMIC RANGE (SFDR), SECOND OR THIRD HARMONIC3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz 25°C 83 dBFS fIN = 170 MHz Full 76 85 dBFS fIN = 340 MHz 25°C 82 dBFS fIN = 450 MHz 25°C 86 dBFS fIN = 765 MHz 25°C 81 dBFS fIN = 985 MHz 25°C 76 dBFS fIN = 1950 MHz 25°C 69 dBFS WORST OTHER (EXCLUDING SECOND OR THIRD HARMONIC)3 VDR Mode (Input Mask Not Triggered) fIN = 10 MHz 25°C −93 dBFS fIN = 170 MHz Full −94 dBFS fIN = 340 MHz 25°C −90 dBFS fIN = 450 MHz 25°C −92 dBFS fIN = 765 MHz 25°C −89 dBFS fIN = 985 MHz 25°C −89 dBFS fIN = 1950 MHz 25°C −85 dBFS TWO-TONE INTERMODULATION DISTORTION (IMD)3, AIN1 AND AIN2 = −7.0 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz 25°C −88 dBFS fIN1 = 338 MHz, fIN2 = 341 MHz 25°C −87 dBFS CROSSTALK4 25°C 95 dB FULL POWER BANDWIDTH 25°C 2 GHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 11 for the recommended settings for full-scale voltage and buffer control settings. 4 Crosstalk is measured at 185 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel. DIGITAL SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance Full LVDS/LVPECL Differential Input Voltage Full 600 1200 1800 mV p-p Input Common-Mode Voltage Full 0.85 V Input Resistance (Differential) Full 35 kΩ Input Capacitance Full 2.5 pF SYSTEM REFERENCE INPUTS (SYNC+, SYNC−) Logic Compliance Full LVDS/LVPECL Differential Input Voltage Full 400 1200 1800 mV p-p Input Common-Mode Voltage Full 0.6 0.85 2.0 V Input Resistance (Differential) Full 35 kΩ Input Capacitance (Differential) Full 2.5 pF LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY) Logic Compliance Full CMOS Logic 1 Voltage Full 0.8 × SPIVDD V Logic 0 Voltage Full 0 0.2 × SPIVDD V Input Resistance Full 30 kΩ |
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