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AD7291BCPZ-RL7 Datasheet(PDF) 21 Page - Analog Devices |
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AD7291BCPZ-RL7 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 29 page  AD7291 Data Sheet Rev. C | Page 20 of 28 HYSTERESIS REGISTER Each analog input channel and the internal temperature sensor has a hysteresis register, which is a 16-bit read/write register. Only the 12 LSBs are used. Bit D15 to Bit D12 are not used in the register and are set to 0s. The hysteresis register stores the hysteresis value, N, when using the limit registers. Each pair of limit registers has a dedicated hysteresis register. The hysteresis value determines the reset point for the ALERT pin if a violation of the limits occurs. For example, if a hysteresis value of eight LSBs is required on the upper and lower limits of Channel 0, the 16- bit word, 0000 0000 0000 1000, must be written to the hysteresis register of CH0, the address of which is 0x06 (see Table 25 and Table 26). During power-up, the hysteresis registers content defaults to all zeros (0x0000). If a hysteresis value is required, that value must be written to the hysteresis register for the channel in question. Table 25. Hysteresis Register (First Read/Write Byte) MSB D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 B11 B10 B9 B8 Table 26. Hysteresis Register (Second Read/Write Byte) LSB D7 D6 D5 D4 D3 D2 D1 D0 B7 B6 B5 B4 B3 B2 B1 B0 ALERT STATUS REGISTER A AND ALERT STATUS REGISTER B (0x1F AND 0x20) The alert status registers are 16-bit, read-only registers that provide information on an alert event. If a conversion result activates the ALERT pin, as described in the Limit Registers (0x04 to 0x1E) section, the alert status register can be read to gain further information. There are two alert status registers in the AD7291; Alert Status Register A, which stores alerts for the analog voltage conversion channels (see Table 27 and Table 28) and Alert Status Register B, which stores alerts for the internal temperature sensor only (see Table 29 and Table 30). Both alert status registers contain two status bits per channel, one corresponding to the DATAHIGH limit and the other to the DATALOW limit. The bit with a status of 1 shows where the violation occurred—that is, on which channel—and whether the violation occurred on the upper or lower limit. If a second alert event occurs on the other channel between receiving the first alert and interrogating the alert status register, the corres- ponding bit for that alert event is also set. The entire contents of the alert status register can be cleared by writing 1 to Bit D2 in the command register. For example, if Bit D14 in Alert Status Register A is set to 1, the lower limit on Channel 7 (Register 0x1A) is violated, while if Bit D11 is set 1, the upper limit on Channel 5 is violated (Register 0x13). The TSENSEHIGH and TSENSE_AVGHIGH alerts are determined by comparison with the TSENSE DATAHIGH register (Register 0x1C). Likewise, the TSENSELOW and TSENSE_AVGLOW alerts are determined by comparison with the TSENSE DATALOW register (Register 0x1D). Table 27. Alert Status Register A (First Read Byte) D15 D14 D13 D12 D11 D10 D9 D8 CH7HIGH CH7LOW CH6HIGH CH6LOW CH5HIGH CH5LOW CH4HIGH CH4LOW Table 28. Alert Status Register A (Second Read Byte) D7 D6 D5 D4 D3 D2 D1 D0 CH3HIGH CH3LOW CH2HIGH CH2LOW CH1HIGH CH1LOW CH0HIGH CH0LOW Table 29. Alert Status Register B (First Read Byte) D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 Table 30. Alert Status Register B (Second Read Byte) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 TSENSE_AVGHIGH TSENSE_AVGLOW TSENSEHIGH TSENSELOW |
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