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Z89321 Datasheet(PDF) 2 Page - Zilog, Inc.

Part # Z89321
Description  16-BIT DIGITAL SIGNAL PROCESSORS
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z89321 Datasheet(HTML) 2 Page - Zilog, Inc.

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Z89321/371/391
16-Bit Digital Signal Processors
Zilog
2
P R E L I M I N A R Y
DS97DSP0100
The Z893XX DSPs are optimized to accommodate ad-
vanced signal processing algorithms. The 24 MIPS (maxi-
mum) operating performance and efficient architecture
provides real-time instruction execution. Compression, fil-
tering, frequency detection, audio, voice detection/synthe-
sis, and other vital algorithms can all be accommodated.
The Z89321/371/391 devices feature an on-board CO-
DEC interface, compatible with 8-bit PCM and 16-bit CO-
DECs for digital audio applications. Additionally, an on-
board wait-state generator is provided to accommodate
slow external peripherals.
For prototypes, as well as production purposes, the
Z89371 member of the DSP product family is a one-time
pro-grammable (OTP) device with a 16 MHz maximum op-
erating frequency.
Notes: All signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
Figure 1. Z89321/371/391 Functional Block Diagram
Program
ROM/OTP
4096x16
Data RAM0
256x16
EA0-2
EXT0-15
/DS
WAIT
RD//WR
Data RAM1
256x16
DDATA
XDATA
PDATA
PADDR
PA0-15
PD0-15
Shifter
Arithmetic
Logic Unit
(ALU)
Program
Control
Unit
INT0-2
HALT
/RESET
CLK
Accumulator
8/16-Bit,
Full Duplex,
10 MBPS
Serial Port
TXD
RXD
SCLK
FS0
FS1
13-Bit Timer
User I/O
UI1-0
UO1-0
XY
Multiplier
P
DP0-3
DP4-6
P2
P2
P1
P1
P0
P0
ADDR
GEN0
ADDR
GEN1


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