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SM65MLVD129DGGR Datasheet(PDF) 8 Page - Texas Instruments |
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SM65MLVD129DGGR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 16 page SN65MLVD128 SN65MLVD129 SLLS586 − MARCH 2004 www.ti.com 8 tc(n) 1/f0 0 V 0 V Period Jitter 0 V Peak to Peak Jitter 1/f0 PRBS INPUT OUTPUT VA −VB VA −VB CLOCK INPUT IDEAL OUTPUT ACTUAL OUTPUT VCC VCC/2 tjit(per) =tc(n) −1/f0 tjit(pp) 0 V VCC VCC/2 0 V VA −VB VA −VB Cycle to Cycle Jitter 0 V VA − VB OUTPUT tc(n) tc(n+1) tjit(cc) = | tc(n) − tc(n+1) | NOTES:D. All input pulses are supplied by an Agilent 8304A Stimulus System. E. The measurement is made on a TEK TDS6604 running TDSJIT3 application software F. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input. G. Peak-to-peak jitter is measured using a 200 Mbps 215−1 PRBS input. Figure 8. Driver Jitter Measurement Waveforms Terminal Functions − SN65MLVD128 PIN TYPE DESCRIPTION NAME NO. TYPE DESCRIPTION 1D 39 Input Data inputs for drivers EN1 − EN8 27, 28, 32, 33, 40, 41, 45, 46 Input Driver enable, active high, individual enables 1A − 8A 2, 4, 8, 10, 14, 16, 20, 22 Output M-LVDS bus noninverting output 1B − 8B 3, 5, 9, 11, 15, 17, 21, 23 Output M-LVDS bus inverting output GND 6, 12, 18, 24, 25, 26, 31, 37, 38, 43, 44 Power Circuit ground VCC 1, 7, 13, 19, 29, 30, 35, 36, 47, 48 Power Supply voltage NC 34, 42 N/A Not connected |
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