SN74LVC1G373

SINGLE DTYPE LATCH

WITH 3STATE OUTPUT

SCES528A − DECEMBER 2003 − REVISED JUNE 2004

1

POST OFFICE BOX 655303

NanoStar

 and NanoFree Packages

Operation

Per JESD 78, Class II

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The SN74LVC1G373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.

When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

While the latch-enable (LE) input is high, the Q output follows the data (D) input. When LE is taken low, the Q

output is latched at the logic level set up at the D input.

NanoStar

 and NanoFree package technology is a major breakthrough in IC packaging concepts, using the

die as the package.

OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING‡

NanoStar

 − WCSP (DSBGA)

0.23-mm Large Bump − YEP

Reel of 3000

SN74LVC1G373YEPR

_ _ _D3_

−40 C to 85 C

NanoFree

 − WCSP (DSBGA)

0.23-mm Large Bump − YZP (Pb-free)

Reel of 3000

SN74LVC1G373YZPR

_ _ _D3_

−40

°C to 85°C

SOT (SOT-23) − DBV

Reel of 3000

SN74LVC1G373DBVR

CA3_

SOT (SOT-23) − DBV

Reel of 250

SN74LVC1G373DBVT

CA3_

SOT (SC-70) − DCK

Reel of 3000

SN74LVC1G373DCKR

D3_

SOT (SC-70) − DCK

Reel of 250

SN74LVC1G373DCKT

D3_

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one

following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition

(1 = SnPb,

Copyright

 2004, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar and NanoFree are trademarks of Texas Instruments.

DBV OR DCK PACKAGE

(TOP VIEW)

1

2

3

6

5

4

LE

GND

D

OE

Q

3

2

1

4

5

6

D

GND

LE

Q

OE

YEP OR YZP PACKAGE

(BOTTOM VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.