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SP3281EBEA Datasheet(PDF) 7 Page - Sipex Corporation |
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SP3281EBEA Datasheet(HTML) 7 Page - Sipex Corporation |
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7 / 15 page  7 Rev. 6/19/03 SP3281EB Intelligent +2.35V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5k Ωpulldownresistorto ground will commit the output of the receiver to a HIGH state. Charge Pump The charge pump is a Sipex–patented design (U.S. #5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump uses a four–phase voltage shifting technique to attain symmetrical ±5.5V power supplies. The internal power supply con- sists of a regulated dual charge pump that provides output voltages ±5.5V regardless of the input voltage (V CC) over the +3.3V to +5.5V range. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations. The charge pump will provide out- put voltage levels of ±4.0V when the input voltage (V CC) is from +3.1V to +2.35V. The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V ( V CC > 3.3V ) and 4.0V (V CC < 3.1V), the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V (V CC > 3.3V) and 4.0V (VCC < 3.1V), the charge pump is disabled. This oscilla- tor controls the four phases of the voltage shifting (Figure 10). A description of each phase follows. Phase 1 (Figure 11) Figure 6. Loopback Test Circuit for RS-232 Driver Data Transmission Rates SP3281EB TxIN TxOUT C1+ C1- C2+ C2- V+ V- VCC 0.1µF 0.1µF 0.1µF + C2 C5 C1 + + C3 C4 + + 0.1µF 0.1µF LOGIC INPUTS VCC 5kΩ RxIN RxOUT LOGIC OUTPUTS SHUTDOWN GND VCC ONLINE 1000pF Figure 10. Charge Pump Waveforms Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V 2 1 T T [] T 2 +6V a) C2+ b) C2- -6V 0V 0V Figure 7. Loopback Test Circuit Result at 120kbps (All Drivers Fully Loaded) Figure 8. Loopback Test Circuit result at 250kbps (All Drivers Fully Loaded) |
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