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IS42S16100C1-7T Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS42S16100C1-7T Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
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1 / 79 page  IS42S16100C1 ISSI® Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. A 07/20/04 Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. July 2004 FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 3.3V power supply • 2.5V VDD option available • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Industrial temperature up to 143 MHz • Package 400-mil 50-pin TSOP II • Lead-free package option DESCRIPTION ISSI’s 16Mb Synchronous DRAM IS42S16100C1 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM PIN CONFIGURATIONS 50-Pin TSOP (Type II) PIN DESCRIPTIONS A0-A11 Address Input A0-A10 Row Address Input A11 Bank Select Address A0-A7 Column Address Input DQ0 to DQ15 Data DQ CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command WE Write Enable LDQM Lower Bye, Input/Output Mask UDQM Upper Bye, Input/Output Mask VDD Power GND Ground VDDQ Power Supply for DQ Pin GNDQ Ground for DQ Pin NC No Connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VDD DQ0 DQ1 GNDQ DQ2 DQ3 VDDQ DQ4 DQ5 GNDQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD GND DQ15 IDQ14 GNDQ DQ13 DQ12 VDDQ DQ11 DQ10 GNDQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND |
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