1.8Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

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9

Detailed Description

The MAX1274/MAX1275 use an input T/H and succes-

sive-approximation register (SAR) circuitry to convert

an analog input signal to a digital 12-bit output. The

serial interface requires only three digital lines (SCLK,

CNVST, and DOUT) and provides easy interfacing to

microprocessors (µPs) and DSPs. Figure 3 shows the

simplified internal structure for the MAX1274/MAX1275.

True-Differential Analog Input T/H

The equivalent circuit of Figure 4 shows the input archi-

tecture of the MAX1274/MAX1275, which is composed

of a T/H, a comparator, and a switched-capacitor digi-

tal-to-analog converter (DAC). The T/H enters its track-

ing mode on the 14th SCLK rising edge of the previous

conversion. Upon power-up, the T/H enters its tracking

mode immediately. The positive input capacitor is con-

nected to AIN+. The negative input capacitor is con-

nected to AIN-. The T/H enters its hold mode on the

falling edge of CNVST and the difference between the

sampled positive and negative input voltages is con-

verted. The time required for the T/H to acquire an input

signal is determined by how quickly its input capaci-

tance is charged. If the input signal’s source imped-

ance is high, the acquisition time lengthens. The

the signal to be acquired. It is calculated by the follow-

ing equation:

the input signal.

impedance below 12Ω does not significantly affect the

ADC’s AC performance.

Input Bandwidth

The ADC’s input-tracking circuitry has a 20MHz small-

signal bandwidth, making it is possible to digitize high-

speed transient events and measure periodic

signals with bandwidths exceeding the ADC’s sam-

pling rate by using undersampling techniques. To

avoid high-frequency signals being aliased into the fre-

quency band of interest, anti-alias filtering is recom-

mended.

Analog Input Protection

Internal protection diodes that clamp the analog input

accurate conversions.

RGND

AIN +

GND

DOUT

SCLK

CNVST

CONTROL

LOGIC AND

TIMING

AIN -

REF

12-BIT

SAR

ADC

MAX1274

MAX1275

T/H

OUTPUT

BUFFER

Figure 3. Functional Diagram

AIN+

AIN-

CONTROL

LOGIC

CAPACITIVE

DAC

COMP

AIN+

AIN-

CONTROL

LOGIC

CAPACITIVE

DAC

COMP

ACQUISITION MODE

HOLD/CONVERSION MODE

Figure 4. Equivalent Input Circuit