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SI4112G-BT Datasheet(PDF) 6 Page - Silicon Laboratories |
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SI4112G-BT Datasheet(HTML) 6 Page - Silicon Laboratories |
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6 / 32 page  Si 41 33 G 6 Rev. 1.1 Figure 1. SCLK Timing Diagram Table 4. Serial Interface Timing (VDD = 2.7 to 3.6 V, TA = –20 to 85°C) Parameter1 Symbol Test Condition Min Typ Max Unit SCLK Cycle Time t clk Figure 1 40 — — ns SCLK Rise Time t r Figure 1 — — 50 ns SCLK Fall Time tf Figure 1 — — 50 ns SCLK High Time t h Figure 1 10 — — ns SCLK Low Time t l Figure 1 10 — — ns SDATA Setup Time to SCLK ↑2 tsu Figure 2 5 — — ns SDATA Hold Time from SCLK ↑2 t hold Figure 2 0 — — ns SENB ↓ to SCLK↑ Delay Time2 ten1 Figure 2 10 — — ns SCLK ↑ to SENB↑ Delay Time2 t en2 Figure 2 12 — — ns SENB ↑ to SCLK↑ Delay Time2 t en3 Figure 2 12 — — ns SENB Pulse Width tw Figure 2 10 — — ns Notes: 1. All timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. Timing is not referenced to 50% level of waveform. See Figure 2. SCLK 80% 20% 50% t r t f t l t clk t h |
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