AD7190_17 datasheet(11/41 Pages) AD

Part #	AD7190

Description	4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC

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AD7190

Data Sheet

Rev. C | Page 10 of 40

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC = NO CONNECT

1

2

3

4

5

6

7

8

9

10

12

11

MCLK2

SCLK

CS

P1/REFIN2(+)

P2

P3

MCLK1

P0/REFIN2(–)

NC

AINCOM

AIN2

AIN1

20

21

22

23

24

19

18

17

16

15

14

13

DOUT/RDY

SYNC

DVDD

AGND

DGND

AVDD

BPDSW

REFIN1(–)

AIN3

AIN4

REFIN1(+)

DIN

AD7190

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

MCLK1

When the master clock for the device is provided externally by a crystal, the crystal is connected between

MCLK1 and MCLK2.

2

MCLK2

Master Clock Signal for the Device. The AD7190 has an internal 4.92 MHz clock. This internal clock can be

made available on the MCLK2 pin. The clock for the AD7190 can be provided externally also in the form of

a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the

MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected.

3

SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be

continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncon-

tinuous clock with the information transmitted to or from the ADC in smaller batches of data.

4

CS

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC

in systems with more than one device on the serial bus or as a frame synchronization signal in

communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode

with SCLK, DIN, and DOUT used to interface with the device.

5

P3

Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND.

6

P2

Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND.

7

P1/REFIN2(+)

Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced

between AVDD and AGND. When REFSEL = 1, this pin functions as REFIN2(+). An external reference can be

applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AVDD and AGND + 1 V. The

nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AVDD, but the part functions with a reference from

1 V to AVDD.

8

P0/REFIN2(−)

Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced

between AVDD and AGND. When REFSEL = 1, this pin functions as REFIN2(−). This reference input can lie

anywhere between AGND and AVDD − 1 V.

9

NC

No Connect. This pin should be tied to AGND.

10

AINCOM

Analog Input AIN1 to Analog Input AIN4 are referenced to this input when configured for pseudo

differential operation.

11

AIN1

Analog Input. It can be configured as the positive input of a fully differential input pair when used with

AIN2 or as a pseudo differential input when used with AINCOM.

12

AIN2

Analog Input. It can be configured as the negative input of a fully differential input pair when used with

AIN1 or as a pseudo differential input when used with AINCOM.

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