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MB90522APFV Datasheet(PDF) 8 Page - Fujitsu Component Limited. |
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MB90522APFV Datasheet(HTML) 8 Page - Fujitsu Component Limited. |
8 / 99 page MB90520A/520B Series 8 s PIN DESCRIPTIONS *1 : FPT-120P-M05 *2 : FPT-120P-M13 (Continued) Pin No. Pin Name Circuit Type Function LQFP-120*1 QFP-120*2 92, 93 X0, X1 A Oscillator pin 74, 73 X0A, X1A B Sub-oscillator pin 89 to 87 MD0 to MD2 C Input pins for setting the operation mode. Connect directly to VCC or VSS. 90 RST C External reset input pin 86 HST C Hardware standby input pin 95 to 101 P00 to P06 D General-purpose I/O ports The settings in the pull-up resistor setup register (RDR0) are enabled when ports are set as inputs. The RDR0 settings are ignored when ports are set as outputs. INT0 to INT6 Event input pins for ch.0 to ch.6 of the DTP/external interrupt circuit 102 P07 D General-purpose I/O port The settings in the pull-up resistor setup register (RDR0) are enabled when ports are set as inputs. The RDR0 settings are ignored when ports are set as outputs. 103 to 110 P10 to P17 D General-purpose I/O ports The settings in the pull-up resistor setup register (RDR1) are enabled when ports are set as inputs. The RDR1 settings are ignored when ports are set as outputs. WI0 to WI7 Event input pins for the wakeup interrupts. 111, 112, 113, 114 P20, P21, P22, P23 E General-purpose I/O ports IC00, IC01, IC10, IC11 Trigger input pins for input capture units (ICU) 0 and 1. Input operates continuously when channels 0 and 1 of input capture units (ICU) 0 and 1 are operating. Accordingly, output to the pins from other func- tions that share this pin must be suspended unless performed intentionally. 115 P24 E General-purpose I/O port AIN0 Also can be used as the count clock A input to 8/16-bit up/down counter/ timer 0. 116 P25 E General-purpose I/O port BIN0 Also can be used as the count clock B input to 8/16-bit up/down counter/ timer 0. 117 P26 E General-purpose I/O port ZIN0 Also can be used as the control clock Z input to 8/16-bit up/down counter/ timer 0. INT7 Event input pin for ch.7 of the DTP/external interrupt circuit |
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