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MAX1277BCTC-T Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX1277BCTC-T Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 10 page 1.5Msps, Single-Supply, Low-Power, True- Differential, 12-Bit ADCs with Internal Reference _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V, VL = VDD, fSCLK = 24MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUTS (AIN+, AIN-) AIN+ - AIN-, MAX1277 0 VREF Differential Input Voltage Range VIN AIN+ - AIN-, MAX1279 -VREF / 2 +VREF / 2 V Absolute Input Voltage Range 0 VDD V DC Leakage Current ±1 µA Input Capacitance Per input pin 16 pF Input Current (Average) Time averaged at maximum throughput rate 75 µA REFERENCE OUTPUT (REF) REF Output Voltage Range Static, TA = +25°C 2.038 2.048 2.058 V Voltage Temperature Coefficient ±50 ppm/°C ISOURCE = 0 to 2mA 0.35 Load Regulation ISINK = 0 to 100µA 1.0 mV/mA Line Regulation VDD = 2.7V to 3.6V, static 0.25 mV/V DIGITAL INPUTS (SCLK, CNVST) Input Voltage Low VIL 0.3 x VL V Input Voltage High VIH 0.7 x VL V Input Leakage Current IIL 0.05 ±10 µA DIGITAL OUTPUT (DOUT) Output Load Capacitance COUT For stated timing performance 30 pF Output Voltage Low VOL ISINK = 5mA, VL ≥ 1.8V 0.4 V Output Voltage High VOH ISOURCE = 1mA, VL ≤ 1.8V VL - 0.5V V Output Leakage Current IOL Output high impedance ±0.2 ±10 µA POWER REQUIREMENTS Analog Supply Voltage VDD 2.7 3.6 V Digital Supply Voltage VL 1.8 VDD V Static, fSCLK = 24MHz 6 8 Static, no SCLK 5 7 Analog Supply Current, Normal Mode IDD Operational, 1.5Msps 7 9 mA fSCLK = 24MHz 2 Analog Supply Current, Partial Power-Down Mode IDD No SCLK 2 mA fSCLK = 24MHz 1 Analog Supply Current, Full Power-Down Mode IDD No SCLK 0.3 1 µA Operational, full-scale input at 1.5Msps 0.3 1 Static, fSCLK = 24MHz 0.15 0.5 Partial/full power-down mode, fSCLK = 24MHz 0.1 0.3 mA Digital Supply Current (Note 8) Static, no SCLK, all modes 0.1 1 µA Positive-Supply Rejection PSR VDD = 3V +20% -10%, full-scale input ±0.2 ±3.0 mV |
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